Priority is claimed from Republic of Korean Patent Application No. 99-63902 filed Dec. 28, 1999, which is incorporated in its entirety by reference.
1. Field of the Invention
The invention relates generally to a code addressable memory (hereinafter called xe2x80x9cCAMxe2x80x9d) cell in a flash memory device, and more particularly to, a CAM cell in a flash memory device capable of improving the operation characteristic of the CAM cell at a low voltage.
2. Description of the Prior Art
A flash memory device is an electrically erasable and programmable non-volatile memory device, which has protection/non-protection function on code information that should be protected when the flash memory product is used and a function allowing a repair, etc. for improving the throughput during product test process. For example, the flash memory device has a function to store the name of the manufacture and its serial number on the product using flash memory device and to store information protecting a specific memory region in a code information of information that should be protected in order to prevent information being deleted by users.
For this, CAM circuits using CAM cells like a flash memory cell is inserted into peripheral circuits. The CAM cell is usually used for the purpose of repair or protect, and CAM data must be easily read-out even at power supply voltage Vcc upon a normal read operation. Then, the conventional CAM cell will be below explained by reference to FIG. 1.
FIGS. 1A and 1B are diagrams for explaining a structure of a code addressable memory cell in a flash memory device, where FIG. 1A shows its layout and FIG. 1B is its schematic view.
As shown, a gate in which a floating gate 12 and a control gate 13 are stacked is formed on a semiconductor substrate 11 and a source S and a drain D are formed on both sides of the semiconductor substrate 11. As such, the conventional CAM cell has a structure like a main cell.
Generally, information stored at the cell is read-out by applying a voltage to the control gate and then sensing the amount of current flowing into the drain D. At this time, in most case, the voltage applied to the control gate usually directly uses the power supply voltage Vcc. However, as most of the current flash memory devices are driven at a low voltage, there is a problem that if the power supply voltage Vcc is directly used, the amount of current flowing into the drain is too small, thus making its sensing difficult.
In other words, upon a read-out of the CAM cell, the conductance Gm of the cell is lowered due to a coupling capacitance of about 0.55 that is generated in the dielectric film between the floating gate 12 and the control gate 13. Due to this, with the threshold voltage VT of about 2.0V like the main cell, the operation voltage of the memory device used as the voltage to the control gate 13 is lowered, thus rapidly reducing the amount of current in the cell. Therefore, as it is difficult to read out certain cell information, a method of sensing data stored in the CAM cell is used by which the cell is inevitably over-erased to lower the threshold voltage of the cell 0V less. However, if the CAM cell is over-erased, there is a problem that it is difficult to store information for a long time due to leak current, etc. from the cell in undesired circumstances in which the cell must be operated at a high temperature and at a high voltage.
It is therefore an object of the present invention to provide a CAM cell in a flash memory device that can be safely operated at a low voltage, by increasing the coupling ratio of a floating gate and a control gate.
In order to accomplish the above object, a CAM cell in a flash memory device according to the present invention is characterized in that it comprises field oxide films formed on a semiconductor substrate in order to define active regions; a floating gate electrically isolated from the semiconductor substrate by a tunnel oxide film, formed to share the active regions of at least more than two isolated by the field oxide film; a dielectric film formed on the floating gate; a control gate formed to overlap with the floating gate, on the dielectric film; a plurality of sources and a plurality of drains isolated by the control gate, each formed in the plurality of active regions; and a source line connecting the plurality of sources and a drain line connecting the plurality of drains.